About
I am a Principal Systems and Software Architect specializing in deterministic, low-latency computing environments, bare-metal embedded runtimes, and high-throughput telecommunications pipelines. My work bridges low-level hardware constraints with high-order algorithmic rigor—from millimeter-wave satellite payloads down to bare-metal audio synthesis primitives.
Over the past decade and a half, I have spearheaded the design and delivery of mission-critical systems across aerospace, communications, and digital signal processing. At Meta R&D, I guided the flight software architecture and ground verification pipelines for mmWave satellite constellations, ensuring sub-millisecond telemetry loops and deterministic link performance under extreme physical and channel constraints.
Outside of commercial telecommunications, I engineer deterministic audio synthesis engines in pure C99, explore array programming paradigms for real-time DSP, and craft minimalist toolchains designed to run with zero unnecessary abstraction. I believe in software that respects memory hierarchies, provides predictable latency bounds, and delivers uncompromising reliability.
Experience
2021 — PRESENT Architected core flight software and ground-station verification suites for next-generation mmWave satellite payloads. Spearheaded deterministic telemetry acquisition protocols, beam-steering state machines, and real-time radio calibration workflows. Collaborated across RF hardware, FPGA, and embedded firmware engineering teams to guarantee sub-millisecond command-and-control dispatch and zero-drop link telemetry.
- C++20
- C99
- Linux RT (PREEMPT_RT)
- mmWave Telemetry
- ZeroMQ
- SDR / GNU Radio
- eBPF
- Python
2017 — 2021 Lead Systems & Infrastructure Architect · Telecommunications & Embedded SystemsEngineered resilient edge computing runtimes and packet processing pipelines for low-latency carrier networking. Directed migration toward custom lock-free memory rings and SIMD-accelerated packet inspection, driving a 4x reduction in 99th-percentile transit latency. Standardized automated HIL (Hardware-in-the-Loop) test harnesses across multi-site lab environments.
- C
- Rust
- DPDK
- POSIX RT
- gRPC
- Automated HIL
- Kernel Networking
2013 — 2017 Senior Embedded Software Engineer · Digital Signal Processing & Real-Time RuntimesDesigned embedded signal processing kernels and DMA-driven audio and RF ingestion pipelines. Authored hard real-time interrupt handlers, circular buffer topologies, and cross-platform synchronization primitives deployed to ARM Cortex-M/A microcontrollers and DSP coprocessors.
- ARM Cortex-M4/M7
- FreeRTOS
- Fixed-Point DSP
- Bare Metal
- I2S / SPI / UART
- C99
Projects
A zero-dependency, pure C99 polyphonic wavetable synthesis engine built for hard real-time audio generation. Features SIMD-vectorized band-limited wavetable interpolation, lock-free ringbuffer command queuing, multi-channel voice stealing, and a decoupled miniaudio backend. Compiles cleanly to native binaries and WebAssembly (WASM/WebAudio) with UDP command dispatch for headless live control.
- Pure C99
- miniaudio
- WebAssembly
- WebAudio
- UDP Dispatch
- SIMD DSP
- Lock-Free Rings
High-performance telemetry multiplexer and frame parser implementing custom binary framing for high-bandwidth satellite downlinks. Leverages memory-mapped rings, zero-copy socket buffers, and lock-free thread topologies to process multi-gigabit streams with deterministic jitter under 15 microseconds.
- C++20
- Kernel Bypass
- Memory-Mapped I/O
- Zero-Copy
- POSIX RT
A concise, array-oriented numerical engine optimized for multi-channel spectral decomposition and polyphase filterbank synthesis. Developed to investigate cache locality patterns and auto-vectorization efficacy across ARM NEON and x86 AVX2 microarchitectures without external BLAS dependencies.
- C99
- AVX2
- ARM NEON
- Fourier Transforms
- Cache Locality